The invention relates to a device for addressing an arbitrary element from a set of Nxe2x89xa62K regular elements or alternatively an element from a set of R less than N redundant elements depending on the binary values of the address bits of a K-bit input address. The address device has a 1-out-of-N decoder, which has K address inputs for receiving the address bits and N outputs for connection to the N regular elements. The device further has R bypass circuits, each of which is assigned to precisely one redundant element. The bypass circuits each have a sensitization circuit for setting the relevant bypass circuit into an active state, a reference bit transmitter for supplying K reference bits which are individually assigned to the K address bits and whose values are programmable by selective destruction or preservation of conductive links or by selective introduction of conducting links, a comparison device which derives K comparison bits from the reference bits and compares them with the respectively assigned address bits and supplies a hit information item if the address bits correspond to a bit combination which is unambiguously related to the bit combination of the comparison bits, and a control circuit, which, upon the appearance of the hit information item, supplies a selection signal which switches off the 1 out-of-N decoder and addresses the assigned redundant element if the relevant bypass circuit is set into the active state. A preferred, but not exclusive, area of application for the invention is the addressing of rows or columns of a memory matrix.
In assemblies that contain a multiplicity of selectively addressable elements and a corresponding addressing device, the functional test carried out after production may reveal that one or more of the elements are defective. Since the direct repair of a defective element is too complex or even impossible in many cases, at least one additional xe2x80x9credundantxe2x80x9d element is provided besides the required number of regular elements as early as during the production of the assembly, which element can serve, as required, as a replacement for a defective element. The number R of redundant elements to be provided is usually less than the number N of regular elements and is dimensioned taking account of the maximum expected defect frequency. All of the redundant elements present are, of course, likewise subjected to a functional test.
The addressing of the elements is typically effected digitally by a multi-bit address using a 1-out-of-N decoder contained in the addressing device, where N is the number of regular elements. If it is desired to fully utilize the available address array, an integer power of 2 is chosen for the number N, that is to say N=2K, where K is the number of bits of the input address for the 1-out-of-N decoder.
In order to replace each defective regular element in a system by a respective defect-free specimen of the R redundant elements, manipulations are performed at the addressing device after the test in order to ensure that, upon the appearance of the input address for a defective regular element, the 1-out-of-N decoder is switched off and the addressing is xe2x80x9cbypassedxe2x80x9d to a respectively selected element of the R redundant elements. For this purpose, the addressing device is additionally provided with R bypass circuits, each of which leads to one of the redundant elements and contains a programmable reference bit transmitter and also a comparison and control logic. Each reference bit transmitter contains a device for providing K bits that can be arbitrarily programmed after the production of the system in order to prescribe a K-bit comparison address. The assigned bypass circuit compares the address with the input address. In the event of correspondence, it switches off the 1-out-of-N decoder and addresses the redundant element assigned to it.
Once the functional test of the assembly has shown which regular and redundant elements are defective, the addresses of the defective regular elements are programmed into the reference bit transmitters. For this purpose, it is possible, of course, to select the reference bit transmitters only of those bypass circuits which lead to defect-free redundant elements. After the programming, it is ensured that when an input address corresponding to a defective element is applied, the 1-out-of-N decoder is inactive, and that the defect-free redundant element selected for this address is addressed instead.
It is generally customary for the reference bit transmitters to be configured in such a way that they can be programmed by so-called xe2x80x9cfusexe2x80x9d technology. For this purpose, the K circuit nodes of each reference bit transmitter, at which the K bits of the comparison address are supplied, are connected to a first of the two logic potentials L or H, which represent the binary values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, via a respective destructible conductive link. Moreover, each of the circuit nodes is connected to the respective other logic potential via a second branch. The configuration is dimensioned in such a way that the circuit node is pulled to the first logic potential in the case of an undestroyed link and is pulled to the other logic potential when the link is destroyed. The links are usually low-value resistors which can be selectively fused e.g. by a laser beam or applied over-voltage (so-called fusible links or xe2x80x9cfusesxe2x80x9d).
Each reference bit transmitter of the type described above can thus be programmed to an arbitrary K-bit address by destruction or preservation of selected specimens of its links in order to ensure that the addressing of the regular element which is normally assigned to the address is bypassed to the redundant element which is assigned to the relevant reference bit transmitter. Even if none of the links in a reference bit transmitter is destroyed, there is a programming to a K-bit address. This would be e.g. the zero address if all the links lead to that logic potential which represents the binary value xe2x80x9c0xe2x80x9d. Thus, a programming state that would not correspond to some of the N input addresses is not possible for a reference bit transmitter.
The above-mentioned functional test may reveal that no or not all the redundant elements are actually required as a replacement (because the number of defective regular elements is less than the number of redundant elements present) or that certain redundant elements are not permitted to be used as a replacement (because they are defective themselves). In these cases, the redundant elements that are not to be used must be prevented from being addressed in an undesirable manner via the assigned bypass circuits. For this reason, a separate sensitization circuit must be provided for each bypass circuit in order that the bypass circuit is put into a active state only when a decision has been taken on account of the functional test that the assigned redundant element is actually to be used as a replacement element.
In the prior art, the above-mentioned sensitization circuits are realized in each case by an addition, superordinate fusible link (xe2x80x9cmaster fusexe2x80x9d) in each bypass circuit. Each of these additional links can be destroyed selectively, in the same way as the other links in the reference bit transmitters. Each additional link is typically disposed in such a way that the relevant bypass circuit can operate only when the additional link is destroyed.
The use of the above-mentioned additional links in accordance with the prior art has disadvantages. This is because destructible links require much space and cannot be miniaturized to the same extent as other circuit components. On the one hand, such a link, particularly if, as is customary, it is formed by a fusible low-value resistor, already takes up a relatively large area for itself. On the other hand, it is necessary to comply with a relatively large distance between the fusible links and also from other circuit sections in order that a targeted destructive access is readily possible without influencing adjacent components. These space requirements lead to problems and various restrictions in particular in the realization of integrated circuits.
It is accordingly an object of the invention to provide an addressing device for selecting regular and redundant elements that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which requires fewer links than before.
With the foregoing and other objects in view there is provided, in accordance with the invention, an addressing device for selecting an element from one of a set of Nxe2x89xa62K regular elements and a set of R less than N redundant elements depending on binary values of address bits of a K-bit input address. The addressing device contains a 1-out-of-N decoder having K address inputs receiving the address bits and N outputs coupled to the N regular elements, and R bypass circuits each coupled to precisely one of the redundant elements. The R bypass circuits are each coupled to the 1-out-of N decoder and each contains a sensitization circuit for setting a respective bypass circuit into an active state, and a reference bit transmitter having programmable links and supplying K reference bits individually assigned to the K address bits and values of the K reference bits being programmable by programming the programmable links. The programmable links are fuses or anti-fuses, and the reference bit transmitter is coupled to the sensitization circuit. The bypass circuit further has a comparison device connected to the reference bit transmitter and derives K comparison bits from the reference bits. The comparison device compares the comparison bits with the address bits and supplies a hit information item if the address bits correspond to a bit combination unambiguously related to the comparison bits. A control circuit receives the hit information item, and upon receiving the hit information item the control circuit supplies a selection signal for switching off the 1-out-of-N decoder and addresses an associated redundant element if the respective bypass circuit is in the active state. The sensitization circuit receives Mxe2x89xa6K preselected reference bits from the reference bit transmitter of the respective bypass circuit and sets the respective bypass circuit into the active state if binary values of the M preselected reference bits received differ from a chosen bit combination.
Accordingly, the invention is realized by the addressing device being configured for selecting the element from a set of Nxe2x89xa62K regular elements or alternatively an element from a set of R less than N redundant elements depending on the binary values of the address bits of a K-bit input address. The addressing device has the 1-out-of-N decoder, which has K address inputs for receiving the address bits and N outputs for connection to the N regular elements. The addressing device further has R bypass circuits, each of which is assigned to precisely one redundant element. The bypass circuits each contain a sensitization circuit for setting the relevant bypass circuit into an active state, a reference bit transmitter for supplying K reference bits which are individually assigned to the K address bits and whose values are programmable by selective destruction or preservation of conductive links or by selective introduction of conductive links, a comparison device for deriving K comparison bits from the K reference bits and compares them with the respectively assigned address bits and supplies a hit information item if the address bits correspond to a bit combination which is unambiguously related to the bit combination of the comparison bits, and a control circuit, which, upon the appearance of the hit information item, supplies a selection signal which switches off the 1-out-of-N decoder and addresses the assigned redundant element if the relevant bypass circuit is set into the active state. According to the invention, each sensitization circuit receives Mxe2x89xa6K preselected reference bits from the reference bit transmitter of the relevant bypass circuit and sets the bypass circuit into the active state if the binary values of the M received reference bits differ from a bit combination chosen.
According to the invention, then, one of the 2M possible combinations of values that the M preselected reference bits of a reference bit transmitter can represent or prescribe is chosen for keeping the bypass circuits deactivated. The xe2x80x9cswitch-offxe2x80x9d bit combination can be chosen as desired, to be precise before the configuration of the addressing device in order that the logic circuits used are configured in an appropriate manner. If, after a test of the regular and redundant elements, a decision has arbitrarily been taken as to which of the defect-free redundant elements are intended to serve as a replacement for defective regular elements, the M preselected reference bits at the reference bit transmitters for the bypass circuits of the remaining redundant elements can be programmed to the switch-off bit combination (or remain unchanged if the original state of the reference bit transmitters is selected as switch-off bit combination), so that the relevant bypass circuits, and specifically only these, remain deactivated. All the other bypass circuits are automatically sensitized by the programming of the M preselected reference bits to combinations of values that differ from the switch-off bit combination. Consequently, the abovementioned additional links that are necessary specifically for the sensitization of the bypass circuits in the case of the prior art can be obviated.
It should be noted that, in an addressing device according to the invention, there are only 2Kxe2x88x922K-M bit combinations available for the programming of sensitized bypass circuits. It is thus possible, as required, to replace any arbitrary element of N regular elements by any arbitrary redundant element if N is not greater than 2Kxe2x88x922K-M. There are applications in which this limitation of the number N should be tolerable, assuming that M is very close to K (e.g. equal to K or equal to Kxe2x88x921).
However, the addressing device according to the invention can also be configured in such a way that this limitation is obviated. A configuration in this respect consists in a device being provided in at least one of the bypass circuits, which device inverts at least one of the M preselected reference bits that are programmed in the assigned reference bit transmitter before it is applied to the comparison device, although the pattern of inversion must not be the same in all the bypass circuits. As will be explained in greater detail, it is possible by virtue of this measure to replace any arbitrary element of a total of N=2K regular elements by an arbitrary element of, in each case, a plurality of redundant elements.
In accordance with an added feature of the invention, the M preselected reference bits are assigned to the same M address bits at each the sensitization circuit.
In accordance with an additional feature of the invention, the comparison device of at least one of the bypass circuits contains an inversion device to generate the comparison bits from the reference bits by transmission of the reference bits with inversion of at least one of the M preselected reference bits, and a pattern according to which the inversion or noninversion of the M preselected reference bits is effected at the comparison device is not the same in all of the bypass circuits.
In accordance with another feature of the invention, a number of different patterns according to which the inversion or noninversion of the M preselected reference bits is affected at the comparison device and is as large as possible, and in that a frequency of the different patterns is as uniform as possible.
In accordance with a further feature of the invention, the sensitization circuit contains a first logic circuit having M inputs and an output supplying a switching bit having a first binary value if the M preselected reference bits differ from the chosen bit combination, and otherwise has a second binary value. The control circuit contains a second logic circuit supplying the selection signal if the switching bit has the first binary value and the hit information item is present.
In accordance with another added feature of the invention, the M inputs of the first logic circuit are fixedly connected to the reference bit transmitter to receive the M preselected reference bits. The second logic circuit has inputs fixedly connected to the outputs of the comparison device and to the first logic circuit to receive the hit information item and the switching bit.
In accordance with another further feature of the invention, M=K, the second logic circuit has a first input and a second input, and the comparison device has K outputs for supplying K output bits corresponding to a predefined bit combination precisely when the address bits correspond to a bit combination which is reversibly unambiguously assigned to a bit combination of the comparison bits. The sensitization circuit has a bi-stable circuit with an output. The bypass circuits each contain a changeover device. The changeover device in a first switching state, connects the inputs of the first logic circuit to the outputs of the comparison device and connects the output of the first logic circuit to the first input of the second logic circuit. The changeover device in a second state, connects the inputs of the first logic circuit to the reference bit transmitter and connects the output of the first logic circuit to the bi-stable circuit. The output of the bi-stable circuit goes to the second binary value if the first logic circuit supplies the first binary value, and goes to the first binary value if the first logic circuit supplies the second binary value. The second logic circuit supplies the selection signal precisely when the first and second inputs of the second logic circuit both receive the first binary value. The changeover device can be temporarily changed over from the first switching state to the second switching state by an initialization pulse.
In accordance with a concomitant feature of the invention, the chosen bit combination of the M preselected reference bits is that which the reference bit transmitter supplies in an original state before a programming of the programmable links.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an addressing device for selecting regular and redundant elements, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.